Aspects of the present invention relate generally to the field of circuit design and test, and more specifically to static timing analysis and simulation of electronics.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the verification, the IC layout may undergo circuit simulation and analysis where the signals between components are tested, for example using static timing analysis (STA) or gate level simulation (GLS).
STA is a method for assessing the timing of a digital circuit using software techniques and certain models that provide relevant characteristics of the circuit design. During STA, models of the expected timing of a digital circuit are created by estimating the expected delay within the circuit, for example, via the anticipated worst case signal path, without requiring a lengthy and cost prohibitive full simulation of the circuit. To accurately estimate the timing of the design, the effects of interference from neighboring nets (aggressors) on each victim net may be estimated.
The behavior of an electronic circuit often depends on various conditions such as temperature or local voltage variations. Consequently, circuit designers typically verify their design under several different conditions, or views, by performing STA for each of the potential different conditions. Each view may have multiple factors, including a constraint file that defines the mode for simulating a condition, for example for a low power or high temperature condition; a library file; and parameters for a resistor-capacitor (RC) reduction, whereby the resistance and capacitance of a network of components and elements are reduced or simplified mathematically. Then to complete the STA, the timing delay of the circuit must be separately calculated for each set of factors, for example, for each unique combination of RC reduction, library file, and input waveform. A distinct factor is sometimes referred to as a corner. Therefore, performing a complete multi-view analysis of even a relatively simple design is excessively time and resource consuming.
Accordingly, there is a need in the art to improve the efficiency of the timing tests across multiple views.